stm32_cec/
lib.rs

1//! HDMI CEC driver for STM32 microcontrollers
2#![no_std]
3#![cfg_attr(docsrs, feature(doc_cfg), feature(doc_auto_cfg))]
4
5mod reg;
6
7pub use reg::{Cfgr, Cr, Regs};
8
9/// Interrupt flags.
10///
11/// All interrupts are cleared by writing `1` to the bit field.
12pub mod irq {
13    /// TX-missing acknowledge error interrupt
14    ///
15    /// In transmission mode, TXACKE is set by hardware to inform application
16    /// that no acknowledge was received.
17    /// In case of broadcast transmission, TXACKE informs application that a
18    /// negative acknowledge was received.
19    /// TXACKE aborts message transmission and clears TXSOM and TXEOM controls.
20    pub const TXACK: u32 = 1 << 12;
21    /// TX-error
22    ///
23    /// In transmission mode, TXERR is set by hardware if the CEC initiator
24    /// detects low impedance on the CEC line while it is released.
25    /// TXERR aborts message transmission and clears TXSOM and TXEOM controls.
26    pub const TXERR: u32 = 1 << 11;
27    /// TX-buffer underrun
28    ///
29    /// In transmission mode, TXUDR is set by hardware if application was not in
30    /// time to load TXDR before of next byte transmission.
31    /// TXUDR aborts message transmission and clears TXSOM and TXEOM control
32    /// bits.
33    pub const TXUDR: u32 = 1 << 10;
34    /// End of transmission
35    ///
36    /// TXEND is set by hardware to inform application that the last byte of the
37    /// CEC message has been successfully transmitted.
38    /// TXEND clears the TXSOM and TXEOM control bits.
39    pub const TXEND: u32 = 1 << 9;
40    /// TX-byte request
41    ///
42    /// TXBR is set by hardware to inform application that the next transmission
43    /// data has to be written to TXDR.
44    /// TXBR is set when the 4th bit of currently transmitted byte is sent.
45    /// Application must write the next byte to TXDR within six nominal data-bit
46    /// periods before transmission underrun error occurs (TXUDR).
47    pub const TXBR: u32 = 1 << 8;
48    /// Arbitration lost
49    ///
50    /// ARBLST is set by hardware to inform application that CEC device is
51    /// switching to reception due to arbitration lost event following the TXSOM
52    /// command.
53    /// ARBLST can be due either to a contending CEC device starting earlier or
54    /// starting at the same time but with higher HEADER priority.
55    /// After ARBLST assertion TXSOM bit keeps pending for next transmission
56    /// attempt.
57    pub const ARBLST: u32 = 1 << 7;
58    /// RX-missing acknowledge.
59    ///
60    /// In receive mode, RXACKE is set by hardware to inform application that no
61    /// acknowledge was seen on the CEC line.
62    /// RXACKE applies only for broadcast messages and in listen mode also for
63    /// not directly addressed messages (destination address not enabled in OAR).
64    /// RXACKE aborts message reception.
65    pub const RXACK: u32 = 1 << 6;
66    /// RX-long bit period error
67    ///
68    /// LBPE is set by hardware in case a data-bit waveform is detected with
69    /// long bit period error.
70    /// LBPE is set at the end of the maximum bit-extension tolerance allowed by
71    /// RXTOL, in case falling edge is still longing.
72    /// LBPE always stops reception of the CEC message.
73    /// LBPE generates an error-bit on the CEC line if LBPEGEN = 1.
74    /// In case of broadcast, error-bit is generated even in case of LBPEGEN = 0.
75    pub const LBPE: u32 = 1 << 5;
76    /// RX-short bit period error
77    ///
78    /// SBPE is set by hardware in case a data-bit waveform is detected with
79    /// short bit period error.
80    /// SBPE is set at the time the anticipated falling edge occurs.
81    /// SBPE generates an error-bit on the CEC line.
82    pub const SBPE: u32 = 1 << 4;
83    /// RX-bit rising error
84    ///
85    /// BRE is set by hardware in case a data-bit waveform is detected with bit
86    /// rising error.
87    /// BRE is set either at the time the misplaced rising edge occurs, or at
88    /// the end of the maximum BRE tolerance allowed by RXTOL, in case rising
89    /// edge is still longing.
90    /// BRE stops message reception if BRESTP = 1.
91    /// BRE generates an error-bit on the CEC line if BREGEN = 1.
92    pub const BRE: u32 = 1 << 3;
93    /// RX-overrun
94    ///
95    /// RXOVR is set by hardware if RXBR is not yet cleared at the time a new
96    /// byte is received on the CEC line and stored into RXD.
97    /// RXOVR assertion stops message reception so that no acknowledge is sent.
98    /// In case of broadcast, a negative acknowledge is sent.
99    pub const RXOVR: u32 = 1 << 2;
100    /// End of reception
101    ///
102    /// RXEND is set by hardware to inform application that the last byte of a
103    /// CEC message is received from the CEC line and stored into the RXD buffer.
104    /// RXEND is set at the same time of RXBR.
105    pub const RXEND: u32 = 1 << 1;
106    /// RX-byte received
107    ///
108    /// The RXBR bit is set by hardware to inform application that a new byte
109    /// has been received from the CEC line and stored into the RXD buffer.
110    pub const RXBR: u32 = 1;
111
112    /// Bitmask of all interrupts.
113    pub const ALL: u32 = TXACK
114        | TXERR
115        | TXUDR
116        | TXEND
117        | TXBR
118        | ARBLST
119        | RXACK
120        | LBPE
121        | SBPE
122        | BRE
123        | RXOVR
124        | RXEND
125        | RXBR;
126}
127
128/// Physical Address
129#[derive(Debug, Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Hash)]
130#[allow(dead_code)]
131pub struct PhysAddr {
132    addr: u32,
133}
134
135#[cfg(feature = "defmt")]
136impl defmt::Format for PhysAddr {
137    fn format(&self, fmt: defmt::Formatter) {
138        defmt::write!(
139            fmt,
140            "{:X}.{:X}.{:X}.{:X}",
141            (self.addr >> 24) as u8,
142            (self.addr >> 16) as u8,
143            (self.addr >> 8) as u8,
144            self.addr as u8,
145        )
146    }
147}
148
149impl core::fmt::Display for PhysAddr {
150    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
151        write!(
152            f,
153            "{:X}.{:X}.{:X}.{:X}",
154            (self.addr >> 24) as u8,
155            (self.addr >> 16) as u8,
156            (self.addr >> 8) as u8,
157            self.addr as u8,
158        )
159    }
160}
161
162/// Logical Address
163#[derive(Debug, Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Hash)]
164#[cfg_attr(feature = "defmt", derive(defmt::Format))]
165#[repr(u8)]
166pub enum LogiAddr {
167    /// Television
168    Tv = 0x0,
169    /// Recording device 1
170    RecDev1 = 0x1,
171    /// Recording device 2
172    RecDev2 = 0x2,
173    /// Tuner 1
174    Tuner1 = 0x3,
175    /// Playback device 1
176    PlaybackDev = 0x4,
177    // Audio system
178    AudioSys = 0x5,
179    /// Tuner 2
180    Tuner2 = 0x6,
181    /// Tuner 3
182    Tuner3 = 0x7,
183    /// Playback Device 2
184    PlaybackDev2 = 0x8,
185    /// Recording Device 3
186    RecDev3 = 0x9,
187    /// Tuner 4
188    Tuner4 = 0xA,
189    /// Playback Device 3
190    PlaybackDev3 = 0xB,
191    /// Reserved 1
192    Rsvd1 = 0xC,
193    /// Reserved 2
194    Rsvd2 = 0xD,
195    /// Free use
196    FreeUse = 0xE,
197    /// Unregistered (as source address) or Broadcast (as destination address).
198    Broadcast = 0xF,
199}
200
201impl From<LogiAddr> for u8 {
202    #[inline]
203    fn from(addr: LogiAddr) -> Self {
204        addr as u8
205    }
206}
207
208impl TryFrom<u8> for LogiAddr {
209    type Error = u8;
210
211    fn try_from(addr: u8) -> Result<Self, Self::Error> {
212        match addr {
213            x if x == Self::Tv as u8 => Ok(Self::Tv),
214            x if x == Self::RecDev1 as u8 => Ok(Self::RecDev1),
215            x if x == Self::RecDev2 as u8 => Ok(Self::RecDev2),
216            x if x == Self::Tuner1 as u8 => Ok(Self::Tuner1),
217            x if x == Self::PlaybackDev as u8 => Ok(Self::PlaybackDev),
218            x if x == Self::AudioSys as u8 => Ok(Self::AudioSys),
219            x if x == Self::Tuner2 as u8 => Ok(Self::Tuner2),
220            x if x == Self::Tuner3 as u8 => Ok(Self::Tuner3),
221            x if x == Self::PlaybackDev2 as u8 => Ok(Self::PlaybackDev2),
222            x if x == Self::RecDev3 as u8 => Ok(Self::RecDev3),
223            x if x == Self::Tuner4 as u8 => Ok(Self::Tuner4),
224            x if x == Self::PlaybackDev3 as u8 => Ok(Self::PlaybackDev3),
225            x if x == Self::Rsvd1 as u8 => Ok(Self::Rsvd1),
226            x if x == Self::Rsvd2 as u8 => Ok(Self::Rsvd2),
227            x if x == Self::FreeUse as u8 => Ok(Self::FreeUse),
228            x if x == Self::Broadcast as u8 => Ok(Self::Broadcast),
229            _ => Err(addr),
230        }
231    }
232}
233
234/// HDMI-CEC driver.
235#[derive(Debug)]
236#[cfg_attr(feature = "defmt", derive(defmt::Format))]
237pub struct Cec<const BASE: usize> {
238    regs: Regs<BASE>,
239}
240
241impl<const BASE: usize> Cec<BASE> {
242    /// Create a new HDMI CEC driver.
243    ///
244    /// # Safety
245    ///
246    /// 1. The HDMI CEC source clock must be enabled.
247    /// 2. The HDMI CEC pin must be configured.
248    /// 3. The HDMI CEC peripheral should be reset before.
249    /// 4. The HDMI CEC registers provided by the PAC should be dropped.
250    /// 5. The generic BASE parameter must be correct or bad things will happen.
251    ///
252    /// # Panics
253    ///
254    /// Panics if reading CFGR does not return the value written.
255    /// This occurs when the HDMI CEC peripheral clocks are not configured
256    /// correctly.
257    ///
258    /// # Example
259    ///
260    /// ```no_run
261    /// use stm32_cec::Cec;
262    ///
263    /// // device specific setup occurs here
264    /// // ...
265    ///
266    /// // valid address for the STM32H7
267    /// let mut cec: Cec<0x40006C00> = unsafe { Cec::<0x40006C00>::new() };
268    /// ```
269    #[inline]
270    pub unsafe fn new() -> Cec<BASE> {
271        let mut regs: Regs<BASE> = Regs { _priv: () };
272        regs.set_cr(Cr::DEFAULT);
273        const MY_CFGR: Cfgr = Cfgr::DEFAULT
274            .set_lstn(true)
275            .set_oar(0x8)
276            .set_lbpegen(true)
277            .set_bregen(true)
278            .set_brestp(true);
279        regs.set_cfgr(MY_CFGR);
280        assert_eq!(Regs::<BASE>::cfgr().oar(), 0x8);
281        regs.set_ier(irq::ALL);
282        regs.set_cr(Cr::EN);
283
284        Cec { regs }
285    }
286
287    fn poll_isr() -> u32 {
288        // TODO: timeout
289        loop {
290            let isr: u32 = Regs::<BASE>::isr();
291            if isr != 0 {
292                Regs::<BASE>::set_isr(isr);
293                return isr;
294            }
295        }
296    }
297
298    fn send_byte(&mut self, src: LogiAddr, dst: LogiAddr, data: u8) -> Result<(), u32> {
299        self.regs.set_txdr((u8::from(src) << 4) | u8::from(dst));
300        self.regs.set_cr(Cr::SOM);
301
302        let isr: u32 = Self::poll_isr();
303        if isr & irq::TXBR == irq::TXBR {
304            self.regs.set_txdr(data);
305            self.regs.set_cr(Cr::EOM);
306            let isr: u32 = Self::poll_isr();
307            if isr & irq::TXEND == irq::TXEND {
308                Ok(())
309            } else {
310                Err(isr)
311            }
312        } else {
313            Err(isr)
314        }
315    }
316
317    /// Power off devices.
318    ///
319    /// # Example
320    ///
321    /// Turn everything off.
322    ///
323    /// ```no_run
324    /// use stm32_cec::{Cec, LogiAddr};
325    ///
326    /// let mut cec = unsafe { stm32_cec::Cec::<0x40006C00>::new() };
327    /// cec.set_standby(LogiAddr::Broadcast, LogiAddr::Broadcast)?;
328    /// # Ok::<(), u32>(())
329    /// ```
330    pub fn set_standby(&mut self, src: LogiAddr, dst: LogiAddr) -> Result<(), u32> {
331        self.send_byte(src, dst, 0x36)
332    }
333
334    /// Power on the TV.
335    ///
336    /// # Example
337    ///
338    /// Turn everything on.
339    ///
340    /// ```no_run
341    /// use stm32_cec::{Cec, LogiAddr};
342    ///
343    /// let mut cec = unsafe { stm32_cec::Cec::<0x40006C00>::new() };
344    /// cec.set_image_view_on(LogiAddr::Broadcast, LogiAddr::Broadcast)?;
345    /// # Ok::<(), u32>(())
346    /// ```
347    pub fn set_image_view_on(&mut self, src: LogiAddr, dst: LogiAddr) -> Result<(), u32> {
348        self.send_byte(src, dst, 0x04)
349    }
350}
stm32_cec/lib.rs

stm32_cec/
lib.rs
