stm32_cec/reg/
cfgr.rs

1/// Signal Free time
2#[derive(Debug, Copy, Clone, Eq, PartialEq)]
3#[cfg_attr(feature = "defmt", derive(defmt::Format))]
4#[repr(u8)]
5pub enum Sft {
6    /// Determined by transmission history.
7    ///
8    /// * 2.5 data-bit periods if CEC is the last bus initiator with
9    ///   unsuccessful transmission
10    ///   (ARBLST = 1, TXERR = 1, TXUDR = 1 or TXACKE = 1)
11    /// * 4 data-bit periods if CEC is the new bus initiator
12    /// * 6 data-bit periods if CEC is the last bus initiator with successful
13    ///   transmission (TXEOM = 1)
14    History = 0x0,
15    /// 0.5 nominal data bit periods
16    Nom0pt5 = 0x1,
17    /// 1.5 nominal data bit periods
18    Nom1pt5 = 0x2,
19    /// 2.5 nominal data bit periods
20    Nom2pt5 = 0x3,
21    /// 3.5 nominal data bit periods
22    Nom3pt5 = 0x4,
23    /// 4.5 nominal data bit periods
24    Nom4pt5 = 0x5,
25    /// 5.5 nominal data bit periods
26    Nom5pt5 = 0x6,
27    /// 6.5 nominal data bit periods
28    Nom6pt5 = 0x7,
29}
30
31/// Configuration register.
32#[derive(Debug, Copy, Clone, Eq, PartialEq)]
33#[cfg_attr(feature = "defmt", derive(defmt::Format))]
34pub struct Cfgr {
35    val: u32,
36}
37
38impl Cfgr {
39    /// Reset value.
40    pub const DEFAULT: Self = Self { val: 0 };
41
42    #[must_use = "set_lstn returns a modified Cfgr"]
43    pub const fn set_lstn(mut self, lstn: bool) -> Self {
44        if lstn {
45            self.val |= 1 << 31;
46        } else {
47            self.val &= !(1 << 31);
48        }
49        self
50    }
51
52    #[must_use]
53    pub const fn oar(&self) -> u16 {
54        ((self.val & 0x7FFF_0000) >> 16) as u16
55    }
56
57    #[must_use = "set_oar returns a modified Cfgr"]
58    pub const fn set_oar(mut self, oar: u16) -> Self {
59        self.val &= 0x8000_FFFF;
60        self.val |= ((oar as u32) & 0x7FFF) << 16;
61        self
62    }
63
64    #[must_use = "set_sftop returns a modified Cfgr"]
65    pub const fn set_sftop(mut self, sftop: bool) -> Self {
66        if sftop {
67            self.val |= 1 << 8;
68        } else {
69            self.val &= !(1 << 8);
70        }
71        self
72    }
73
74    #[must_use = "set_brdnogen returns a modified Cfgr"]
75    pub const fn set_brdnogen(mut self, brdnogen: bool) -> Self {
76        if brdnogen {
77            self.val |= 1 << 7;
78        } else {
79            self.val &= !(1 << 7);
80        }
81        self
82    }
83
84    #[must_use = "set_lbpegen returns a modified Cfgr"]
85    pub const fn set_lbpegen(mut self, lbpegen: bool) -> Self {
86        if lbpegen {
87            self.val |= 1 << 6;
88        } else {
89            self.val &= !(1 << 6);
90        }
91        self
92    }
93
94    #[must_use = "set_bregen returns a modified Cfgr"]
95    pub const fn set_bregen(mut self, bregen: bool) -> Self {
96        if bregen {
97            self.val |= 1 << 5;
98        } else {
99            self.val &= !(1 << 5);
100        }
101        self
102    }
103
104    #[must_use = "set_brestp returns a modified Cfgr"]
105    pub const fn set_brestp(mut self, brestp: bool) -> Self {
106        if brestp {
107            self.val |= 1 << 4;
108        } else {
109            self.val &= !(1 << 4);
110        }
111        self
112    }
113
114    #[must_use = "set_rxtol returns a modified Cfgr"]
115    pub const fn set_rxtol(mut self, rxtol: bool) -> Self {
116        if rxtol {
117            self.val |= 1 << 3;
118        } else {
119            self.val &= !(1 << 3);
120        }
121        self
122    }
123
124    #[must_use = "set_sft returns a modified Cfgr"]
125    pub const fn set_sft(mut self, sft: Sft) -> Self {
126        self.val &= 0xFFFF_FFF8;
127        self.val |= sft as u32;
128        self
129    }
130}
131
132impl Default for Cfgr {
133    fn default() -> Self {
134        Self::DEFAULT
135    }
136}
137
138impl From<u32> for Cfgr {
139    #[inline]
140    fn from(val: u32) -> Self {
141        Self { val }
142    }
143}
144
145impl From<Cfgr> for u32 {
146    #[inline]
147    fn from(cfgr: Cfgr) -> Self {
148        cfgr.val
149    }
150}
stm32_cec/reg/cfgr.rs

stm32_cec/reg/
cfgr.rs
