stm32_cec/reg/
mod.rs

1mod cfgr;
2mod cr;
3
4pub use cfgr::Cfgr;
5pub use cr::Cr;
6
7/// HDMI-CEC register access.
8#[derive(Debug)]
9#[cfg_attr(feature = "defmt", derive(defmt::Format))]
10pub struct Regs<const BASE: usize> {
11    pub(crate) _priv: (),
12}
13
14impl<const BASE: usize> Regs<BASE> {
15    // register addresses
16    const CR: *const u32 = BASE as *const u32;
17    const CFGR: *const u32 = (BASE + 0x04) as *const u32;
18    const TXDR: *mut u32 = (BASE + 0x08) as *mut u32;
19    const RXDR: *const u32 = (BASE + 0x0C) as *const u32;
20    const ISR: *const u32 = (BASE + 0x10) as *const u32;
21    const IER: *const u32 = (BASE + 0x14) as *const u32;
22
23    /// Read the command register.
24    #[inline]
25    pub fn cr() -> Cr {
26        unsafe { Self::CR.read_volatile() }.into()
27    }
28
29    /// Write the command register.
30    #[inline]
31    pub fn set_cr(&mut self, cr: Cr) {
32        unsafe { (Self::CR as *mut u32).write_volatile(u32::from(cr) & 0b111) }
33    }
34
35    /// Read the configuration register.
36    #[inline]
37    pub fn cfgr() -> Cfgr {
38        unsafe { Self::CFGR.read_volatile() }.into()
39    }
40
41    #[inline]
42    pub fn set_cfgr(&mut self, cfgr: Cfgr) {
43        unsafe { (Self::CFGR as *mut u32).write_volatile(u32::from(cfgr) & 0xFFFF_01FF) }
44    }
45
46    /// Write the TX data register.
47    #[inline]
48    pub fn set_txdr(&mut self, data: u8) {
49        unsafe { Self::TXDR.write_volatile(data as u32) }
50    }
51
52    /// Read the RX data register.
53    #[inline]
54    pub fn rxdr(&mut self) -> u8 {
55        unsafe { Self::RXDR.read_volatile() as u8 }
56    }
57
58    /// Read the interrupt status register.
59    #[inline]
60    pub fn isr() -> u32 {
61        unsafe { Self::ISR.read_volatile() }
62    }
63
64    #[inline]
65    pub fn set_isr(isr: u32) {
66        unsafe { (Self::ISR as *mut u32).write_volatile(isr & super::irq::ALL) }
67    }
68
69    /// Read the interrupt enable register.
70    #[inline]
71    pub fn ier() -> u32 {
72        unsafe { Self::IER.read_volatile() }
73    }
74
75    /// Write the interrupt enable register.
76    #[inline]
77    pub fn set_ier(&mut self, ier: u32) {
78        unsafe { (Self::IER as *mut u32).write_volatile(ier & super::irq::ALL) }
79    }
80}
stm32_cec/reg/mod.rs

stm32_cec/reg/
mod.rs
